GOPHERSPACE.DE - P H O X Y
gophering on ams1.josuah.net
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josuah.net
What is Josuah up to?
https://josuah.net/blog/atom.xml
USB Standards
https://josuah.net/blog/2022-02-24/
2022-02-24T00:00:00Z
2022-02-24T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Address decoding and multiplexer
https://josuah.net/blog/2022-04-22/
2022-04-22T00:00:00Z
2022-04-22T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Wishbone B4: Standard or Pipelined?
https://josuah.net/blog/2022-04-25/
2022-04-25T00:00:00Z
2022-04-25T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
FPGA ←SPI→ MCU: Crossing Clock Domains
https://josuah.net/blog/2022-05-11/
2022-05-11T00:00:00Z
2022-05-11T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Interacting with FPGA hardware
https://josuah.net/blog/2022-05-12/
2022-05-12T00:00:00Z
2022-05-12T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Different Clock Domains With Verilator
https://josuah.net/blog/2022-05-18/
2022-05-18T00:00:00Z
2022-05-18T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Interface in Open-Source SystemVerilog Synthesis
https://josuah.net/blog/2022-07-06/
2022-07-06T00:00:00Z
2022-07-06T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
SystemVerilog structs as ersatz to interafces
https://josuah.net/blog/2022-07-08/
2022-07-08T00:00:00Z
2022-07-08T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Sequential signals may hide combinational ones
https://josuah.net/blog/2022-07-20/
2022-07-20T00:00:00Z
2022-07-20T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net
Memes: #fpga #verilog #yosys #nextpnr
https://josuah.net/blog/2022-07-22/
2022-07-22T00:00:00Z
2022-07-22T00:00:00Z
Josuah Demangeon
mailto:me@josuah.net